This application claims the benefit of Korean Patent Application No. P98-44180, filed on Oct. 21, 1998.
1. Field of the Invention
This invention relates to a circuit for driving a display device of active matrix type, and more particularly to a shift register for driving pixel rows in a liquid crystal display.
2. Description of the Prior Art
Generally, a conventional liquid crystal display device used in a television or a computer includes a liquid crystal matrix having liquid crystal cells arranged at intersections of data lines and select or gate lines. The select lines are horizontal lines (i.e., row lines) of the liquid crystal matrix, which are sequentially driven with a shift register. As shown in FIG. 1, the conventional shift register includes n stages 21 to 2n connected in cascade and simultaneously connected, via output lines to 41 to 4n, to n row lines ROW1 to ROWn or gate lines, respectively. A scanning pulse SP is inputted to the first stage 21, and output signals g1 to gnxe2x88x921 of the previous stages are inputted to the 2nd to nth stages 22 to 2n, respectively. Also, n stages 21 to 2n receive two clock signals out of three clock signals C1 to C3. Each of the n stages 21 to 2n drives an associated row line ROWi connected to a pixel train with the two clock signals and the output signals of previous stages or with the two clock signals and the scanning pulse SP.
As shown in FIG. 2, each of the stages 21 to 2n includes a fifth NMOS transistor T5 for applying a high logic voltage signal to an output line 4i, and a sixth NMOS transistor T6 for applying a low logic voltage signal to the output line 4i. If a high logic level of (ixe2x88x921)th row line input signal gixe2x88x921 is applied from the previous stage 2ixe2x88x921, then first and fourth NMOS transistors T1 and T4 are turned on. As seen from FIG. 3, a high logic level of third clock signal C3 is synchronized with the (ixe2x88x921)th row line input signal gixe2x88x921 and applied to a third NMOS transistor T3 , thereby turning on the third NMOS transistor T3 . The third and fourth NMOS transistors T3 and T4 are a so-called xe2x80x98ratioed logicxe2x80x99 which are set to an appropriate ratio of resistance values in such a manner that a voltage at a second node P2 becomes a low level when the third and fourth NMOS transistors T3 and T4 are simultaneously turned on. Accordingly, when (ixe2x88x921)th row line input signal gixe2x88x921 is applied, a low logic level voltage emerges at the second node P2. At this time, the second and sixth NMOS transistor T2 and T6 are turned off by a low logic level voltage from the second node P2. A first node P1 is charged into a high logic level voltage by a supply voltage VDD when the first NMOS transistor T1 is turned on and the second NMOS transistor T2 is turned off When the high logic level voltage at the first node P1 arrives at a threshold voltage thereof, the fifth NMOS transistor T5 is turned off. At this time, since the first clock signal C1 remains at a low logic level, a low logic level voltage emerges at the output line 4i.
If the first clock signal C1 has a high logic level voltage during a time interval when a voltage at the first node P1 remains at a high logic level, then the output line 4i becomes a high logic level by a high logic level first clock signal C1 applied via the fifth NMOS transistor T5. Accordingly, a high logic level output signal Vout emerges at the output line 4i. At this time, since the output line 4i and the first node P1 are coupled as shown in FIG. 4 with a parasitic capacitance Cgs existing between the gate and the source of the fifth NMOS transistor T5, a voltage at the first node P1 is bootstrapped into a high logic voltage level. Accordingly, the high logic level voltage of the first clock signal C1 is applied to the output line 4i almost without a loss. Such a bootstrap system is used to compensate a voltage loss caused by a threshold voltage generated at a circuit including NMOS transistors.
Also, if the first clock signal C1 is changed from a high logic level voltage into a low logic level voltage, a voltage Vout at the output line 4i drops into a low logic level voltage because the fifth NMOS transistor T5 is in a turned-off state. Furthermore, since the first and fourth NMOS transistors T1 and T4 are turned off by the (ixe2x88x921)th row line input signal gin having a low logic level voltage in such a manner to be supplied with no voltage, a voltage level at the first node P1 also drops slowly. In such a state, if the third clock signal C3 has a high logic level voltage, then the third NMOS transistor T3 is turned off to thereby begin charging the second node P2 into a high logic level voltage with the aid of the supply voltage VDD applied via the third NMOS transistor T3. The sixth NMOS transistor T6 is turned on by a voltage signal higher than its threshold voltage applied from the second node P2 to discharge a voltage charged on the output line 4i toward a ground voltage VSS. As a result, a voltage at the row line ROWi connected to the output line 4i maintains a low logic level.
In order to operate such a shift register normally, a resistance ratio of the third and fourth NMOS transistors T3 and T4 serving as a ratioed logic must be set accurately. In other words, in order to generate a low logic level voltage at the second node P2 when the third clock signal C3 having a high level voltage and the (ixe2x88x921)th row line input signal gixe2x88x921 are applied simultaneously to the gates of the third and fourth NMOS transistors T3 and T4, a channel width of the fourth NMOS transistor T4 must be about ten times larger than that of the third NMOS transistor T3. If characteristics of the NMOS transistors T3 and T4 become non-uniform, a current ratio of the third NMOS transistor T3 to the fourth NMOS transistor T4 varies. In this case, the shift register fails to operate properly.
Further, since a direct current flows continuously at the third and fourth NMOS transistors T3 and T4 when the third and fourth NMOS transistors T3 and T4 are simultaneously turned on by the third clock signal C3 and the (ixe2x88x921)th row line input signal gixe2x88x921, the characteristics of the third and fourth NMOS transistors T3 and T4 are susceptible to deterioration by overcurrent. Also, if the first clock signal C1 is changed from a low logic level voltage into a high logic level voltage during an interval when a voltage at the first node P1 is in a state of high logic level, then a rising width in a bootstrapped voltage at the first node P1 becomes different in accordance with a parasitic capacitance value of the fifth NMOS transistor T5 and a change in the parasitic capacitance at the first node P1. The voltage rising width at the first node P1 is as described in the following formula (1):                               Δ          ⁢                      xe2x80x83                    ⁢          Vp1                =                                            CAP              +                              C                OX                                                                    C                L1                            +              CAP              +                              C                OX                                              ⁢          Δ          ⁢                      xe2x80x83                    ⁢          Vout                                    (        1        )            
wherein xcex94Vp1 and xcex94Vout represent a voltage change amount at the first node P1 and a voltage change amount at the output line 4i, respectively, and CL and Cox represents a parasitic capacitance at the first node P1 and a parasitic capacitance of the fifth NMOS transistor T5, respectively. The parasitic capacitance Cox of the fifth NMOS transistor T5 is equal to a sum of parasitic capacitance Cgs between the gate and the source thereof and parasitic capacitance Cds between the drain and the gate thereof.
As seen from the formula (1), since a rising width in a voltage at the first node P1 is changed by the capacitance CL at the first node P1 and the parasitic capacitance Cox of the fifth NMOS transistor T5, it is difficult to set a characteristic of shift register accurately. Moreover, in the shift register of FIG. 2, the output voltage Vout at the output line 4i is distorted because a voltage at the second node P2 also is raised by a parasitic capacitance between the gate and the drain of the sixth NMOS transistor T6 as a voltage at the output line 4i changes into a high logic level.
Accordingly, it is an object of the present invention to provide a shift register that is adaptive for preventing a change in a circuit characteristic caused by a change in a parasitic capacitance.
A further object of the present invention is to provide a shift register that is adaptive for preventing a deterioration in a circuit characteristic caused by overcurrent.
A still further object of the present invention is to provide a shift register that is adaptive for minimizing a voltage loss caused by the threshold voltage.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other objects of the invention, a shift register according to one aspect of the present invention includes a plurality of stages which are commonly connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines.
Each of the plurality of stages included in the shift register according to one aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; and means for raising a voltage of the first control signal.
Each of the plurality of stages included in the shift register according to another aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of the first control signal; and means for discharging the second control signal during a time interval when the first control signal is enabled.
Each of the plurality of stages included in the shift register according to still another aspect of the present invention comprises output circuit means including a pull-up transistor and a pull-down transistor, said pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the row line, and a first control electrode; said pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line, and a second control electrode; input circuit means being responsive to the scanning signal for generating a first control signal to be applied to the first control electrode, and responsive to a second clock signal having a delayed phase in comparison to the first clock signal for generating a second control signal to be applied to the second control electrode; means for raising a voltage of the first control signal; and means for accelerating a discharging speed at the row line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.